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This paper reviews the main challenges for the TCAD of 14nm Fully-Depleted Silicon-On-Insulator (FDSOI) technology performance assessment. Thanks to a multi-scale approach combining extensive electrical characterization and advanced solvers simulations, ensuring deep physical insight, we provide TCAD simulation framework for device layout optimization,(More)
This paper investigates the mobility `apparent' channel length dependency in nanometric devices. Based on a series of current and capacitance measurements, we report clear (V<sub>G</sub>)<sup>-1</sup> dependencies of the access resistance in Bulk but also in FDSOI devices. We show that the &#x03BC;<sub>eff</sub>-L<sub>eff</sub> degradation observed at small(More)
A lot of works have been done to propose and study alternative devices for future electronics. Between the possible candidates (Tunneling FETs, stacked nanowires...), Reconfigurable FET (RFET) appears as an interesting option to achieve reprogrammable logic in future circuits. The first step to evaluate the potentialities of new devices at circuit level is(More)
Tunnel FETs (TFET) are promising candidates for integration in logic circuits at very low supply voltages. We report here a SPICE compact model that describes all regimes of the TFET transistor. The current contribution from source and drain sides is described by an original set of equations including the electrostatic behavior and the effect of superlinear(More)
Stress engineering is a powerful tool to enhance nanoscale device performances. In this study we developed a methodology of 14nm strained pMOS FDSOI device mechanical simulation in order to carefully evaluate different stress effects on device performances. Mechanical simulation results are presented for different process solutions, such as Gate-First (GF)(More)
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