J. Garcia-Lamont

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This paper describes a digital real time image demosacking implementation for high definition video cameras. It comprises one buffer for three pixel rows and one interpolator based on bilinear interpolation. It has been implemented with HDL-Verilog and mapped onto Virtex-4 XC4VLX25 from Xilinx; for a clock frequency of 150 MHZ, its throughput is 72 frames(More)
This paper shows the results obtained experimentally by controlling the speed of a DC motor using different wavelets (Morlet, RASP1, RASP2, RASP3, POLY-WOG1, POLYWOG3, POLYWOG4 and Shannon) in an auto-tuning wavenet PID controller. Such controller tunes online the proportional, integral and derivative gains of a classical discrete PID controller, through(More)
The object the present work is to present a model for a retinal prosthesis. The translation of an algorithm on the standard technology of silicon sets a trade off between accurate of model and feasibility to implementation. That is, a high accurately of the model, normally results in more complexity, and therefore minus feasibly its implementation in(More)
A digital pixel for binary morphological image processing is presented. The pixel is designed to be integrated into a vision chip with parallel architecture, in order to compute edge segmentation. The pixel contains 11 transistors working with analog signal and 20 transistor working with digital signal; pixel layout size is 115.2 mum times 89.4 mum; fill(More)
The present work shows, implementation of neural ICA algorithms with multiple inputs using VHDL Design in a Field Programmable Gate Array (FPGA). We designed an architecture modular using INFOMAX algorithm in order to add n inputs for audio signals. Some simulations results using VHDL are presented using music and voice recorded. The study of performance is(More)
This paper presents a vision chip for laser spot detection. The sensor has an architecture that comprises a 64x64 pixel array with a pixel pitch of 38.6μm x 30.8μm and fill factor of 30% and two position processors that deliver coordinate position for both axes. Under maximum speed condition, power consumption was 103mW, where maximum(More)
An analog architecture of optic signal processing is presented in this work, with the goal to emulate one of the much processes involved in a biological retina. Here we have considered that the receptive field is the main unit of processing in the visual system. So, the proposed architecture tries to give partial solution to the properties of a receptive(More)
Here, a characterization methodology for integrated silicon-based photo-devices is presented. Devices are phototransistors (“P+/N-Well/P-substrate”) and photodiodes (“N-Well/P-substrate”) with similar sizes, (9µm×9µm). They were integrated in a 1.5µm CMOS technology through MOSIS. Through these(More)
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