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- J Greg Nash
- 2001

The problem of rapidly generating optimal parallel circuit implementations from high level, formal descriptions of affinely indexed algorithms is addressed here in the context of reconfigurable FPGA-based computing. A specialized software tool, SPADE, is described that will take a user's high level code description of his algorithms and automatically… (More)

- J Greg Nash, Centar, N J N K N N Z K X N E K N Π ∑ ∑ ∑ ∑ − − − − − − − − − − − − = = = = = = = = = = = = Or Z Cx, Z X Z X Z X Z X Z X Z X Z X Z X Z X
- 2003

A novel, scalable parallel FFT architecture mapping is described here that supports transform lengths which aren't powers of two or four, that provides low latency as well as high throughput, that can do both 1-D and 2-D discreet Fourier transforms (DFTs), that is ideally suited to today's complex FPGA architectures, that possesses all the regularity and… (More)

- J. Greg Nash
- 2001

A specialized ASIC/FPGA CAD tool is described that will take a user's high level code description of an algorithm and automatically generate abstract latency-optimal systolic arrays. Several new systolic mapping examples of the Lyapunov matrix equation (find X, given AX+XB=C) obtained using this CAD tool are described. Introduction A systolic implementation… (More)

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