J.F. de Marneffe

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The Ni-silicide phase formation in FUSI gates was investigated comparing soak and spike anneals for the first RTP step. From both physical analysis on blanket wafers and electrical measurements on nMOS FUSI/HfSiON device it is found that the RTP1 temperature process window (PW) to obtain NiSi or Ni<sub>3</sub>Si<sub>2</sub> at the FUSI/dielectric interface(More)
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