J. F. Buller

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32-nm complementary metal oxide semiconductor (CMOS) silicon-on-insulator (SOI) with metal gate high-k (MGHK) offers high performance and low power for microprocessors. However, these advanced technologies come with challenges for analog design. Many of the stressor performance elements can adversely impact analog circuit behavior. For example, band-gap(More)
Gate length (L/sub GATE/) scaling to reduce CMOS delay is becoming problematic due to high gate currents from thin gate dielectrics, process induced L/sub GATE/ variation, and high channel dopings that reduce carrier mobility. These issues have led to tailoring of transistor architecture components and a "multiple everything" approach (e.g. multiple oxides,(More)
Partial depleted (PD) SOI technologies have reached maturity for production of high speed, low power microprocessors. The paper will highlight several challenges found during the course of development for bringing 40nm gate length (L/sub GATE/) PD SOI transistors into volume manufacturing for high-speed microprocessors. The key innovations developed for(More)
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