J. F. Buller

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What is it about the Europeanisation of British monetary policy that merits attention? From a superficial glance at the subject, one might conclude: ‘not a lot’. In policy terms, this Europeanisation process as represented by sterling’s membership of the European Exchange Rate Mechanism (ERM) appears to have lasted a mere two years. As is often the case,(More)
Partial depleted (PD) SOI technologies have reached maturity for production of high speed, low power microprocessors. The paper will highlight several challenges found during the course of development for bringing 40nm gate length (L/sub GATE/) PD SOI transistors into volume manufacturing for high-speed microprocessors. The key innovations developed for(More)
Gate length (L/sub GATE/) scaling to reduce CMOS delay is becoming problematic due to high gate currents from thin gate dielectrics, process induced L/sub GATE/ variation, and high channel dopings that reduce carrier mobility. These issues have led to tailoring of transistor architecture components and a "multiple everything" approach (e.g. multiple oxides,(More)
What has sometimes been called the ‘standard’ argument for fatalism never achieved the critical popularity of Richard Taylor’s (1962) infamous argument. But it has enjoyed far greater longevity. In De Fato Cicero (1960) tells us it was known in ancient Greece as the ‘idle argument’, for it purports to show the futility of attempting to control one’s fate(More)
What is it about the Europeanisation of British monetary policy that merits attention?1 From a superficial glance at the subject, one might conclude: ‘not a lot’. In policy terms, this Europeanisation process as represented by sterling’s membership of the European Exchange Rate Mechanism (ERM) appears to have lasted a mere two years. As is often the case,(More)
32-nm complementary metal oxide semiconductor (CMOS) silicon-on-insulator (SOI) with metal gate high-k (MGHK) offers high performance and low power for microprocessors. However, these advanced technologies come with challenges for analog design. Many of the stressor performance elements can adversely impact analog circuit behavior. For example, band-gap(More)
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