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This paper describes a 2 GHz active variable gain low noise amplifier (VGLNA) in a 0.18-mum CMOS process. The VGLNA provides a 50 Omega input impedance and utilizes a tuned load to provide high selectivity. The VGLNA achieves a maximum small signal gain of 16.8 dB and a minimum gain of 4.6 dB with good input return loss. In the high gain and the low gain(More)
This paper describes a CMOS LNA for Bluetooth/IEEE802.11b front-end receiver in a TSMC 0.18-mum process. The LNA provides a 50Omega input impedance and utilizes a tuned load to provide high selectivity. The LNA achieves a maximum small signal gain of 18.9 dB within 1-dB compression point (iCP<sub>1dB</sub>) of -13.2 dBm. The LNA acquires an NF of 2 dB with(More)
Software defined radio (SDR) has gained much interest in recent years due to the advancements in FPGA technology. FPGA provides the capability of programming analog components (Mixers, PLL, Filters etc...) which were traditionally implemented in hardware. In this paper digital functional blocks that need to be programmed in FPGA core are designed and(More)
New system-on-chip (SoC) design techniques are necessary to address the communication requirements for future SoC. The currently used bus-centered approach becomes an inappropriate choice because of its limitation as a shared medium that restricts the scalability of the communication architecture. Also, long bus wires result in performance degradation due(More)
This paper describes a 5 GHz fully differential variable gain low noise amplifier (VGLNA) in a 0.18-mum CMOS process. The LNA provides a 50-Omega input impedance and utilizes a tuned load to provide high selectivity. The VGLNA achieves a maximum small signal gain of 12.34 dB within 1-dB compression point (iCP<sub>1db</sub>) of -12.0 dBm and a minimum gain(More)
This paper describes a CMOS mixer for a WCDMA front-end receiver in 0.18-mum CMOS. The mixer achieves a conversion gain of 16.6 dB and a double side band (DSB) NF of 13.8 dB. The mixer's IIP3 is 12.12 dBm. The achieved low noise figure, gain and overall IIP3 fulfill the specifications for a UMTS mixer design. The mixer consumes 5 mA of current from a 1.8-V(More)
The precision vertex tracker, based on the technology of active CMOS pixel sensors, is a proposed addition to the tracking system of the STAR experiment . The proposed tracker consists of two cylindrical layers formed by 24 ladders. Each ladder contains a row of 10 monolithic CMOS detector chips and each chip has a 640 /spl times/ 640 array of 30 micron(More)
Reconfigurable architectures bridge the gap between ASICs and general-purpose microprocessors, achieving potentially higher performance than general-purpose microprocessors while maintaining a higher level of flexibility than ASICs. This paper first reviews the current research activities in reconfigurable platform architectures and identifies areas that(More)
This paper describes a 1.5-V 5 GHz I/Q down conversion mixer in a 0.18-mum CMOS process. The mixer achieves a conversion gain of 12.7 dB within 1-dB compression point (iCP<sub>1dB</sub>) of -15.83 dBm. It also achieves a double side band (DSB) NF of 13.5 dB. The mixer's IIP3 is -5.94 dBm. The mixer consumes only 5.72 mA of current from a 1.5-V power supply.
In today's world of advanced technology numerous applications are computational intensive. This created an opportunity for the development of new System-on-Chip (SoC) design techniques to allow easy IP cores (Intellectual Property cores) re-use and integration under time-to-market pressure. New System-on-Chip (SoC) design techniques are necessary to address(More)