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We present experimental and simulation results on single-event transients in an analog subsystem for satellite electronic equipment. Investigations based on worst-case transient events, simulated with transistor-level circuit models, suggest design modifications for hardening.
Direct observation of fast-transient single event signatures often involves considerable uncertainty due to the limitations of monitoring circuitry. A built-in-self-test circuit for the measurement of single-event transients (SET) has been implemented in a 45 nm partially depleted silicon-on-insulator technology that allows for the extraction of(More)
Two 32nm SOI single-event upset test chips have been irradiated at LBNL and TAMU heavy ion test facilities. The test chips include unhardened and RHBD designs such as DICE, LEAP DICE, and stacking devices. SEU cross-section data are presented for the hardened and unhardened flip-flop designs across test facility, beam tune, angle of incidence, and clock(More)
We have applied a 3OkeV focused ion beam QTB) as a diagnostic tool for isolating and probing packaged-part devices for the extraction of analog single-event-transient (ASET) model parameters. Complete ASET circuit modeling of the OP27 highspeed, low-noise operational amplifier and comparisons to laser and broad-beam experiments are presented.
In this work, we investigate how externally applied mechanical stress impacts the total dose hardness and enhanced low-dose-rate sensitivity of linear bipolar ICs fabricated with different passivation layers. To determine the effects of externally applied stress and/or radiation exposure on the current gain, various compressive or tensile stresses were(More)
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