J. C. Tinoco

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During the last years, high-k dielectrics have been studied intensively looking for an alternative material to replace the SiO2 films as gate dielectric in MOS transistors. Different materials and structures have been proposed. An important concern not yet solved, is the interfacial quality between high-k materials and silicon substrate. For this reason,(More)
Triple-Gate FinFETs have been demonstrated to be promising to push further the down scaling of the CMOS technology, thanks to their high immunity against the so-called short channel effects. However, due to their three-dimensional (3-D) architecture, strong degradation of their analog characteristics has been reported, basically due to large extrinsic(More)
Triple-Gate FinFETs have been demonstrated to be promising to push further the down scaling of CMOS technology, because of their high immunity against the so-called short channel effects. However, due to their three-dimensional (3-D) architecture, strong degradation of their analog characteristics has been reported, basically due to large extrinsic(More)
In this paper, a semi-analytical extrinsic gate capacitance model for Triple Gate FinFET, based on three-dimensional numerical simulations, is presented. The model takes into account the source/drain electrode and contact areas. It includes 5 capacitance components that describe the different fringing electrical couplings that exist inside the FinFET(More)
Adequate modelling of MOS transistors for RF applications requires the accurate extraction of the extrinsic series resistances. In this paper, we fairly compare several RF extraction methods based on simulation results provided by an accurate foundry compact model of advanced RF MOSFETs. We present the relative sensitivity of each published RF(More)
In recent years, FinFET transistors have received much interest thanks to the better immunity to short-cannel effects [1]. DC characteristics of FinFETs at high temperature were recently reported in [2]. RF characteristics of Bulk Si MOSFETs measured at low temperature (77K) have been presented in a few papers [3]-[4]. To the knowledge of the authors, the(More)
A methodology to properly establish an accurate SOI FinFET compact model through SPICE simulator is presented. This compact model is implemented in Verilog-A to simulate the performance of RF circuits based on SOI FinFET technology. It predicts well static behavior of the transistor and circuit, as well as their small-signal RF behavior by modeling the(More)
The dependence with the measurement frequency observed in the Capacitance-Voltage characteristics of Metal-Insulator-Semiconductor structures using an amorphous oxide semiconductor material is presented and analyzed. It is demonstrated by simulation that the effect is due to the Distribution of States (DOS) present in the energy gap of the semiconductor(More)