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This paper describes a novel gate-level dual-threshold static power optimization methodology (GDSPOM), which is based on the static timing analysis (STA) technique for designing high-speed low-power SOC applications using 90 nm multi-threshold complementory metal oxide semiconductor (MTCMOS) technology. The cell libraries come in fixed threshold—high Vth(More)
This paper presents a low-power design technique (LPDT) for a low-voltage pipelined microprocessor circuit via multi-threshold CMOS (MTCMOS) techniques. Using the MTCMOS LPDT, a pipelined MIPS microprocessor circuit having 220,000 transistors with 5 stages per instruction has been optimized in terms of power consumption using standard threshold-SVT and high(More)
Hot carrier stress (HCS) induces significant degradation on the performance of 65 nm RF n-MOSFET with minimum poly length (L<sub>poly</sub>). Although the cutoff frequency (F<sub>t</sub>) is very high (~212 GHz) for these devices, the high HCS degradation poses a challenge for RF application. Additional effort will be needed to improve the process and/or(More)
This paper reports the subthreshold characteristics of the SOI NMOS device considering the floating body effects. As verified by the experimentally measured data, as the channel length is scaled down from 1&#x03BC;m to 120nm, the subthreshold slope is steeper as a result of the dominance of the parasitic BJT in the thin film. For the channel length further(More)
Algorithmic composition, a form of artificial creativity, is not a new concept. Music is arguably the most mathematical art form in existence and since there has been music, composers have tried to develop processes to supersede the human creative process. Different structures were developed over time; notable examples include i) counterpoint in the Baroque(More)
This paper reports modeling the parasitic bipolar device in the 40nm PD SOI NMOS device considering the floating body effect. Using a unique extraction method, the function of the parasitic bipolar device during transient operations could be modeled. During the turn-on transient by imposing a step voltage from 0V to 2V at the gate, the case with a slower(More)