The division operation has proved to be a much more difficult function to generate efficiently than the other elementary arithmetic operations. This is due primarily to the need to test the result of one iteration before proceeding to the next. The technique described in this contribution reduces the iteration time by the use of a redundant quotientâ€¦ (More)

Although the advent of microprocessors has put considerable computing power in the hands of large numbers of users, there is still an important group who have yet to benefit fully from large scale integration. As a step in the direction of rectifying this situation, a highly flexible chip set is being designed, with a view to reducing the cost of a powerfulâ€¦ (More)

An expandable multiplier chip has been designed on an ECL gate array using a novel serial-parallel algorithm. Systems applications of these devices will offer 64 Ã— 64-bit multiplication in 140 nsecs plus a reduction in chip count over conventional systems.

In this paper radix-4 algorithms for square root and division are developed. The division algorithm evaluates the more useful function xz/y. These algorithms are shown to be suitable for implementing as a unified hardware unit which evaluates square root, division, and multiplication. Cost reductions in the hardware are obtained by use of gate arrays. Aâ€¦ (More)