Jürgen Rauscher

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A pipelined folding-interpolating ADC with a distributed quantizer is presented. The low-mismatch analog frontend provides for excellent SFDR and SNDR without calibration or digital post processing. The algorithm of the digital coder relaxes the requirements on the interface between analog core and digital coder. The single-core ADC achieves 7.3 ENOB and a(More)
Complex integrated systems contain more and more on-chip components which exchange data and access memories via buses. To consider parasitic effects on bus structures during the early design phase appropriate models and wiring methods must be available. A RC-Pi model is proposed to model the load of a bus driver cell that also considers capacitive coupling(More)
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