Jörg Weller

Learn More
Memory interfaces for high-speed graphics systems have reached the 4 to 6 Gb/s/pin regime with GDDR4 and the introduction of GDDR5 [1-4] at chip densities up to 512Mb. To satisfy the demand for even higher data bandwidths and increased memory densities, more advanced design techniques are required. In this paper, a 7Gb/s/pin 1Gb GDDR5 DRAM with an array(More)
  • 1