Jörg Schepers

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Higher-dimensional orthogonal packing problems have a wide range of practical applications, including packing, cutting, and scheduling. In the context of a branch-and-bound framework for solving these packing problems to optimality, it is of crucial importance to have good and easy bounds for an optimal solution. Previous e orts have produced a number of(More)
Higher-dimensional orthogonal packing problems have a wide range of practical applications, including packing, cutting, and scheduling. Previous efforts for exact algorithms have been unable to avoid structural problems that appear for instances in twoor higher-dimensional space. We present a new approach for modeling packings, using a graph-theoretical(More)
Abst rac t . The d-dimensional orthogonal knapsack problem (OKP) has a wide range of practical applications, including packing, cutting, and scheduling. We present a new approach to this problem, using a graphtheoretical characterization of feasible packings. This characterization allows us to deal with classes of packings that share a certain(More)
Higher-dimensional orthogonal packing problems have a wide range of practical applications, including packing, cutting, and scheduling. Combining the use of our data structure for characterizing feasible packings with our new classes of lower bounds, and other heuristics, we develop a two-level tree search algorithm for solving higher-dimensional packing(More)
Recent generations of Field Programmable Gate Arrays (FPGA) allow the dynamic reconfiguration of cells on the chip during run-time. For a given problem consisting of a set of tasks with computation requirements modeled by rectangles of cells, several optimization problems such as finding the array of minimal size to accomplish the tasks within a given time(More)
Recon gurations J urgen Teich Computer Engineering University of Paderborn, Germany S andor P. Fekete Department of Mathematics TU Berlin, Germany Jorg Schepers IBM Germany K oln, Germany Abstract Recent generations of Field Programmable Gate Arrays (FPGA) allow the dynamic recon guration of cells on the chip during run-time. For a given problem(More)