Jérôme Rocheteau

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The need for the B method first appeared in industry, and several commercial tools have been developed to support this formalism. However, few of these tools allow reasoning on the formalism itself or on its possible extensions. This article presents an open-source platform, with a focus on the platform's core component, the BCaml project. The tools(More)
This paper aims at presenting TTC TermSuite: a tool suite for multilingual terminology extraction from comparable corpora. This tool suite offers a userfriendly graphical interface for designing UIMA-based tool chains whose components (i) form a functional architecture, (ii) manage 7 languages of 5 different families, (iii) support standardized file(More)
This paper deals with a formal method for the study of the backward reachability analysis applied on Colored Petri Nets (CPN). The proposed method proceeds in two steps : 1) it translates CPN to terms of the Multiplicative Intuitionistic Linear Logic (MILL); 2) it proves sequents by constructing proof trees. The translation from CPN to MILL must respect(More)
This paper aims at presenting Reifier, a tool for prototyping modules of JEE applications by the means of a model-driven development. Web services are de ned as parametric components which enables to express web service patterns, to verify them formally and to reuse them in other contexts. Although Reifier requires developers to implement components(More)
This paper highlights the benefits within the Green Computing metrics measurement context from the MEASURE ITEA 3 project (Measuring Software Engineering) Project French cluster. It presents the Structured Metrics Meta-model (SMM) used as a standardized language and its implementation within the Softeam’s Modelio modelling and ICAM’s EMIT, a set of tools(More)
We aim at building a formal framework to specify, describe and verify circuits embedded into safety critical systems. We extend current verification techniques that make possible to prove circuit design correctness is such a way that enables to prove that circuits behave safely. Correct circuits are only checked design fault free whereas circuits are safe(More)
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