Jérôme Juillard

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We present a new approach to parameter estimation problems based on binary measurements, motivated by the need to add integrated low-cost self-test features to microfabricated devices. This approach is based on the use of original weighted least-squares criteria: as opposed to other existing methods, it requires no dithering signal and it does not rely on(More)
This paper deals with the initialization of the BIMBO method, a deterministic identification method based on binary observation, for the (self-) test of integrated electronic and electromechanical systems, such as MEMS. Finding an adequate starting point for the parameter estimation algorithm may be crucial, depending on the chosen model parameterization.(More)
In the field of resonant NEMS design, it is a common misconception that large-amplitude motion, and thus large signal-to-noise ratio, can only be achieved at the risk of oscillator instability. In the present paper, we show that very simple closed-loop control schemes can be used to achieve stable largeamplitude motion of a resonant structure, even when(More)
This brief addresses the problem of clock generation and distribution in globally synchronous locally synchronous chips. A novel architecture of clock generation based on network of coupled all-digital PLLs is proposed. Solutions are proposed to overcome the issues of stability and undesirable synchronized modes (modelocks) of high-order bidirectional PLL(More)
In this paper, the problem of active clock distribution network synchronization is considered. The network is made of identical oscillators interconnected through a distributed array of phase-locked-loops (PLLs). The problem of the PLL network design is reformulated, from a control theory point of view, as a control law design for a distributed multi-agent(More)
This paper analyses the stability of the synchronized state in Cartesian networks of identical all-digital phase-locked loops (ADPLLs) for clock distribution applications. Such networks consist in Cartesian grids of digitally-controlled oscillator nodes, where each node communicates only with its nearest neighbors. Under certain conditions, we show that the(More)
in this paper, we describe an architecture of a distributed ADPLL (All Digitall Phase Lock Loop) network based on bang-bang phase detectors that are interconnected asymmetrically. It allows an automatic selection between two operating modes (uniand bidirectional) to avoid mode-locking phenomenon, to accelerate the network convergence and to improve the(More)