Jérôme Dubois

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Recommended by Dragomir Milojevic A high-speed analog VLSI image acquisition and low-level image processing system are presented. The architecture of the chip is based on a dynamically reconfigurable SIMD processor array. The chip features a massively parallel architecture enabling the computation of programmable mask-based image processing in each pixel.(More)
Raw output data from image sensors tends to exhibit a form of bias due to slight on-die variations between pho-todetectors, as well as between amplifiers. The resulting bias, called fixed pattern noise (FPN), is often corrected by subtracting its value, estimated through calibration, from the sensor's raw signal. This paper introduces an on-line scene-based(More)
A high speed VLSI image sensor including some pre-processing algorithms is described in this paper. The sensor implements some low-level image processing in a massively parallel strategy in each pixel of the sensor. Spatial gradients, various convolutions as Sobel or Laplacian operators are described and implemented on the circuit. Each pixel includes a(More)
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