Jérôme Dubois

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— A high speed analog VLSI image acquisition and pre-processing system has been designed and fabricated in a 0.35 µm standard CMOS process. The chip features a massively parallel architecture enabling the computation of programmable low-level image processing in each pixel. Extraction of spatial gradients and convolutions such as Sobel or Laplacian filters(More)
For a knot K in S 3 and a regular representation ρ of its group G K into SU(2) we construct a non abelian Reidemeister torsion form on the first twisted cohomology group of the knot exterior. This non abelian Reidemeister torsion form provides a volume form on the SU(2)-representation space of G K (see Section 5). In another way, we construct according to(More)
373 arXiv version: fonts, pagination and layout may vary from AGT published version A volume form on the SU(2)–representation space of knot groups JÉRˆOME DUBOIS For a knot K in S 3 we construct according to Casson—or more precisely taking into account Lin's [13] and Heusener's [10] further works—a volume form on the SU(2)–representation space of the group(More)
A high speed VLSI image sensor including some preprocessing algorithms is described in this paper. The sensor implements some low-level image processing in a massively parallel strategy in each pixel of the sensor. Spatial gradients, various convolutions as Sobel or Laplacian operators are described and implemented on the circuit. Each pixel includes a(More)
Acoustic focusing experiments usually require large arrays of transducers. It has been shown by Etaix et al. [J. Acoust. Soc. Am. 131, 395-399 (2012)] that the use of a cavity allows reducing this number of transducers. This paper presents experiments with Duralumin plates (the cavities) containing scatterers to improve the contrast of focusing. The use of(More)
Recommended by Dragomir Milojevic A high-speed analog VLSI image acquisition and low-level image processing system are presented. The architecture of the chip is based on a dynamically reconfigurable SIMD processor array. The chip features a massively parallel architecture enabling the computation of programmable mask-based image processing in each pixel.(More)
A new mechanism causing deterioration of the threshold voltage matching performance of MOSFETs is described. We demonstrate that this effect depends on several fundamental CMOS device architecture aspects such as the source/drain implant energies, the gate layer thickness, a gate top oxide layer thickness and the poly-silicon gate morphology. It is(More)