Jérémie Guillot

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An original technique to transform functional representation of the design into a structural representation in form of a data flow graph (DFG) is described. A canonical, word-level data structure, Taylor Expansion Diagram (TED), is used as a vehicle to effect this transformation. The problem is formulated as that of applying a sequence of decomposition cuts(More)
—An efficient graph-based method to optimize polynomial expressions in data-flow computations is presented. The method is based on the factorization, common-subexpression elimination , and decomposition of algebraic expressions performed on a canonical Taylor expansion diagram representation. It targets the minimization of the latency and hardware cost of(More)
This paper describes an efficient graph-based method to optimize data-flow expressions for best hardware implementation. The method is based on factorization, common subexpression elimination (CSE) and decomposition of algebraic expressions performed on a canonical representation, Taylor Expansion Diagram. The method is generic, applicable to arbitrary(More)
This paper describes an efficient method to perform fac-torization of DSP transforms based on Taylor Expansion Diagram (TED). It is shown that TED can efficiently represent and manipulate mathematical expressions. We demonstrate that it enables efficient factorization of arithmetic expressions of DSP transforms, resulting in a simplification of the(More)
ŠCONSIDERABLE PROGRESS has been made during the past two decades in behavioral and high-level synthesis (HLS), making it possible to synthesize designs specified using standard programming languages such as C, C++, and System C. 1 HLS tools automatically generate an RTL specification of the circuit from a bit-accurate algorithm description for a given(More)
— This paper describes an agent oriented framework supporting bio-inspired mechanisms which takes profit of the intrinsic hardware parallelism of the pervasive platform developed within the Perplexus IST European project. The proposed framework is a flexible and modular means to describe and simulate complex phenomena such as biologically plausible neural(More)
Implementing image processing applications in embedded systems is a difficult challenge due to the drastic constraints in terms of cost, energy consumption and real time execution. Reconfigurable archi-tectures are good candidates to take-up this challenge and especially when the architecture is able to support different word-lengths of pixel through(More)
—This paper presents a new unified design flow developed within the Perplexus project that aims to accelerate parallelizable data-intensive applications in the context of ubiquitous computing. This contribution relies on the JubiTool: a set of integrated tools (JubiSplitter, JubiCompiler, UbiAssembler), allowing respectively to extract, compile and assemble(More)
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