Izuchukwu Nwachukwu

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While higher associativities are common at L-2 or Last-Level cache hierarchies, direct-mapped and low associative caches are still used at L-1 level. Lower associativities result in higher miss rates, but have fast access times on hits. Another issue that inhibits cache performance is the non-uniformity of accesses exhibited by most applications: some sets(More)
Article history: Received 9 February 2011 Received in revised form 19 December 2011 Accepted 19 December 2011 Available online 10 January 2012 0045-7906/$ see front matter 2011 Elsevier Ltd doi:10.1016/j.compeleceng.2011.12.008 q Reviews processed and approved for publication ⇑ Corresponding author. E-mail addresses: krishna.kavi@unt.edu, kavi@cs There have(More)
The trend in architectural designs has been towards using simple cores for building multicore chips, instead of a single complex out-of-order (OOO) core, due to the increased complexity and energy requirements of out of order processors. Multicore chips provide better performance when compared with OOO cores while executing parallel applications. However,(More)
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