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Complex signal processing algorithms are specified in floating point precision. When their hardware implementation requires fixed point precision, type refinement is needed. The paper presents a methodology and design environment for this quantization process. The method uses independent strategies for fixing MSB and LSB weights of fixed point signals. It(More)
A C++ based programming environment for the design of complex high speed ASICs is presented. The design of a 75 Kgate DECT transceiv er is used as a driv er example. Compact descriptions, combined with efficient sim ulationand syn thesis strategies are essen tial for the design of such a complex system. It is sho wn how a C++ programming approach(More)
Invited Paper In this paper we reflect on the nature of digital telecommuni-cation systems. We argue that these systems require, by nature, a heterogeneous specification and an implementation with heterogeneous architectural styles. CoWare is a hardware/software co-design environment based on a data model that allows to specify, simulate, and synthesize(More)
The implementation of embedded networked appliances requires a mix of processor cores and HW accelerators on a single chip. When designing such complex and heterogeneous SoCs, the HW / SW partitioning decision needs to be made prior to refining the system description. With OCAPI-xl, we developed a methodology in which the partitioning decision can be made(More)
The design of analog front-ends of digital telecommunica-tion transceivers requires simulations at the architectural level. The nonlinear nature of the analog front-end blocks is a complication for their modeling at the architectural level, especially when the nonlinear behavior is frequency dependent. This paper describes a method to derive a bottom up(More)
In this paper the design problems encountered when designing heterogeneous systems are studied and solutions to these problems are proposed. It will be shown why a single heterogeneous specification method ranging from concept to architecture is required and why it should cover issues as modularity, design for reuse, reuse of designs and reuse of design(More)
Substrate noise caused by large digital circuits will degrade the performance of analog circuits located on the same substrate. To simulate this performance degradation, the total amount of generated substrate noise must be known. Simulating substrate noise generated by large digital circuits is however not feasible with existing circuit simulators and(More)
Standard interfaces for hardware reuse are currently deened at the structural level. In contrast to this, our contribution deenes the reuse interface at the behavioral register-transfer RT level. This promotes direct reuse of function-ality and avoids the integration problems of structural reuse. We present an object oriented reuse interface in C++ and show(More)