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Complex signal processing algorithms are specified in floating point precision. When their hardware implementation requires fixed point precision, type refinement is needed. The paper presents a methodology and design environment for this quantization process. The method uses independent strategies for fixing MSB and LSB weights of fixed point signals. It(More)
In this paper the design problems encountered when designing heterogeneous systems are studied and solutions to these problems are proposed. It will be shown why a single heterogeneous specification method ranging from concept to architecture is required and why it should cover issues as modularity, design for reuse, reuse of designs and reuse of design(More)
ion. • On the other hand, in spite of faster time to market and exponentially growing complexity, the size of the design teams does not seem to grow. All the above leads to a need to increase design productivity by at least one order of magnitude by the end of the decade. Clearly this requires a design technology that enables a seamless transition from a(More)
Substrate noise caused by large digital circuits will degrade the performance of analog circuits located on the same substrate. To simulate this performance degradation, the total amount of generated substrate noise must be known. Simulating substrate noise generated by large digital circuits is however not feasible with existing circuit simulators and(More)
Advanced multimedia systems intrinsically have a high memory cost, making the design of high performance, low power solutions a real challenge. Rather than spending most effort on implementation platform dependent optimization steps, we advocate a methodology and tool that involve C-level platform independent optimizations. This approach is applied to an(More)
It has extensively been demonstrated that system-level methodologies are crucial for the realization of low power implementations of data dominated systems. In this paper, we focus on the low power design problem for multimedia systems, for which the data transfer and storage cost is indeed dominant. We present the implications of integrating a system-level(More)
The implementation of embedded networked appliances requires a mix of processor cores and HW accelerators on a single chip. When designing such complex and heterogeneous SoCs, the HW / SW partitioning decision needs to be made prior to refining the system description. With OCAPI-xl, we developed a methodology in which the partitioning decision can be made(More)
The design of analog front-ends of digital telecommunication transceivers requires simulations at the architectural level. The nonlinear nature of the analog front-end blocks is a complication for their modeling at the architectural level, especially when the nonlinear behavior is frequency dependent. This paper describes a method to derive a bottom-up(More)