Ivan Siu-Chuang Lu

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A quad-band GSM/GPRS/EDGE receiver, implemented in 65 nm CMOS, complies with the ETSI standard without the need of external SAW filters. By exploring the properties of passive mixers and current-mode operation from RF to baseband, the receiver can achieve a SAW-filter-like selectivity with inexpensive on-chip components such as resistors and capacitors. In(More)
This paper presents the power and performance analysis of a digital, direct sequence ultra-wideband (DS-UWB) receiver operating in the 3 to 4 GHz band. The signal to noise and distortion ratio (SNDR) and bit error rate (BER) were evaluated with varying degrees of front-end linearity and analog to digital converter (ADC) accuracy. The analysis and simulation(More)
A 40 nm CMOS transceiver supports 10 bands of HSPA+ and quad-band GSM/EDGE occupying 6.2 mm<sup>2</sup> of a Modem SoC. The TX supports up to 11 Mb/s HSUPA with minimal analog filtering and &lt;;35 mA battery current DG-09 weighted. Receive diversity with dual cell HSDPA supports up to 42 Mb/s downlink. The RX path is inductorless and achieves -111 dBm(More)
This paper presents for the first time the circuit parameter analysis of a digital Multiband-UWB transceiver, encompming a novel low-power subhand generator. This subband generator is capable of producing multiple frequency bands, enabling subband generation From 3 to l0GHz with nanosecond switching times. The circuit analysis of the complete transceiver is(More)
The paper presents a performance analysis of direct sequence ultra wideband (DS-UWB) systems operating with non-linear receiver front-ends. Following this analysis, we propose the novel use of pulse doublets to mitigate non-linearity induced distortion. The signal-to-noise-and-distortion ratio (SNDR) and bit error rate (BER) are evaluated with varying(More)
This brief presents a robust, power efficient CMOS frequency divider for the 5-GHz UNII band. The divider operates as a voltage controlled ring oscillator with the output frequency modulated by the switching of the input transmission gate. The divider, designed in a 0.25m SOS-CMOS technology, occupies 35 25 m and exhibit a operating frequency of 5.6 GHz(More)
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