Ivan Saraiva Silva

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Abstract: This paper presents the architecture and the VHDL design of a Two Dimensional Discrete Cosine Transform (2-D DCT) for JPEG image compression. This architecture is used as the core of a JPEG compressor and is the critical path in JPEG compression hardware. The 2-D DCT calculation is made using the 2-D DCT separability property, such that the whole(More)
This work presents a memory hierarchy model for a full search motion estimation core. The motion estimation is the most complex module in a video encoder requiring intensive computation and high memory bandwidth, mainly when the focus is high definition videos. The proposed memory hierarchy model is based on a data reuse scheme considering the full search(More)
The increase of stream-based applications complexity has demanded hardware more flexible and able to reaching higher performance. Reconfigurable architectures have been showed significant progresses in exploiting the parallelism of these applications. This paper presents RoSA, a coarse-grained reconfigurable architecture that combines compilation techniques(More)
Cache coherency and cache consistency in NoC-based heterogeneous platforms are still open problems. Current works addressing platform design avoid this issue either by proposing cacheless implementations or using snoopy protocols over buses. This paper addresses the cache coherence problem in a NoC-based MPSoC platform, focusing the communication(More)
This paper analyzes the utilization of a network on chip (NoC) as the communication sub-system of a reconfigurable/parallel architecture. A router was designed and implemented in SystemC to analyze the NoC. With this routers the NoCX4 was created and simulated using coarse-grained reconfigurable microprocessor as processing nodes. To perform the simulation(More)
This paper presents the proposal and design of architectures to be used in the last stage of the JPEG compression: the entropy coding. This paper focuses in the compression of gray scale images and color images. The entropy coder architectures were described in VHDL and were synthesized for an Altera Flex10kE FPGA. The entropy coder for gray scale images(More)
This paper presents the design and implementation of a multiplierless JPEG compressor for gray scale images. The modules of this architecture were fully pipelined and targeted to FPGA device implementation. The designed architectures are detailed in this paper and they were described in VHDL, simulated and physically mapped to Altera Flex10KE FPGAs. The(More)