Ivan Saraiva Silva

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The increase of stream-based applications complexity has demanded hardware more flexible and able to reaching higher performance. Reconfigurable architectures have been showed significant progresses in exploiting the parallelism of these applications. This paper presents RoSA, a coarse-grained reconfigurable architecture that combines compilation techniques(More)
Cache coherency and cache consistency in NoC-based heterogeneous platforms are still open problems. Current works addressing platform design avoid this issue either by proposing cacheless implementations or using snoopy protocols over buses. This paper addresses the cache coherence problem in a NoC-based MPSoC platform, focusing the communication(More)
This paper analyzes the utilization of a network on chip (NoC) as the communication sub-system of a reconfigurable/parallel architecture. A router was designed and implemented in SystemC to analyze the NoC. With this routers the NoCX4 was created and simulated using coarse-grained reconfigurable microprocessor as processing nodes. To perform the simulation(More)
This paper presents new techniques for architecture and performance driven compilation of SW programs into RW (reconfigurable HW). These new techniques effectively improve on the complex resource sharing approaches typical of high-level synthesis algorithms, which are efficient for layout flexible ASICs but are clearly not adequate for reconfigurable(More)
The X4CP32 is a novel coarse RPU runtime-reconfigurable general purpose microprocessor. It consists of 3 programming levels, based on a hierarchic array of easily and quickly reconfigurable entities. It brings a new concept of runtime reconfiguration and programming, which is it's main strength. Although it's effectiveness in heavy arithmetic applications,(More)