Ivan P. Radivojevic

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This paper describes an exact symbolic formulation of control-dependent, resource-constrained scheduling. The technique provides a closed-form solution set in which all satisfying schedules are encapsulated in a compressed OBDD-based representation. This solution format greatly increases the flexibility of the synthesis task by enabling incremental(More)
Optimization of hardware resources for conditional data-flow graph behavior is particularly important when conditional behavior occurs in cyclic loops and maximization of throughput is desired. In this paper, an exact and efficient conditional resource sharing analysis using a guardbased control representation is presented. The analysis is transparent to a(More)
This paper describes a symbolic formulation that allows incorporation of speculative operation execution (preexecution) in an exact control-dependent scheduling of arbitrary forward branching control/data paths. The technique provides a closed form solution set in which all satisfying schedules are encapsulated in a compressed OBDD-based representation. To(More)
This paper describes a new exact formulation of control/data-flow scheduling. Unlike current techniques, a closed form solution set is generated in which all satisfying schedules for arbitrary forward branching control/data paths and resource constraints are encapsulated in a compressed OBDD-based representation. A robust, iterative construction strategy is(More)
It has been generally assumed that recently introduced symbolic techniques are applicable only to small scheduling problems. This report demonstrates that applicability of these techniques can be extended to larger dataflow graphs by: (i) using Zero-Suppressed BDDs, (ii) applying a set of interior constraints that reduce the size of intermediate solutions,(More)
This paper describes an exact symbolic formulation of resource-constrained scheduling which allows speculative operation execution in arbitrary forward-branching control/data paths. The technique provides a closed-form solution set in which all satisfying schedules are encapsulated in a compressed OBDD-based representation. An iterative construction method(More)
In ASIC construction, design changes can occur at all phases of the product development cycle. When changes occur late in the development cycle, say after datapath synthesis and verification, it can be very expensive not to maintain a significant portion of the pre-existing design. However, changes in this environment require accommodation of the(More)
This thesis describes an exact symbolic formulation of control-dependent, resource-constrained scheduling. The technique provides a closed-form solution set in which all satisfying schedules are encapsulated in a compressed Binary Decision Diagram (BDD) representation. This solution format greatly increases the flexibility of the synthesis task by enabling(More)
Digital signal processors (DSPs) are suitable for a wide variety of computationally intensive real-time applications. This paper describes the architectural features of DSPs for intelligence and control applications, and the node configuration of the IX-n generalpurpose neurocomputer, based on the commercially available DSP. DSPs provide high computing(More)
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