Ivan D. Castellanos

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A System on Chip (SoC) library for MOSIS scalable CMOS rules has been developed. It is intended for use with Synopsys and Cadence Design Systems Electronic Design Automation tools. Students can also use layout tools for semi-custom designs and insert them with the proposed design flow. Scalable submicron rules are used for the cell library, allowing it to(More)
This paper discusses an open source, variation aware Process Design Kit (PDK), based on Scalable CMOS design rules, down to 45nm, for use in VLSI research, education and small businesses. This kit includes all the necessary layout design rules and extraction command decks to capture layout dependent systematic variation and perform statistical circuit(More)
Decimal multiplication has grown in interest due to the recent announcement of new IEEE 754R standards and the availability of high-speed decimal computation hardware. Prior research enabled partial products to be coded more efficiently for their use in radix 10 architectures. This paper clarifies previous techniques for partial product reduction using(More)
This paper discusses an extension to an open source, variation aware Process Design Kit (PDK), based on Scalable CMOS design rules. This PDK is designed for 45nm feature sizes and is utilized for use in VLSI research, computer architecture, education and small businesses. This kit includes all the necessary layout design rules and extraction command decks(More)
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