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Secure processors enable new applications by ensuring private and authentic program execution even in the face of physical attack. In this paper we present the AEGIS secure processor architecture, and evaluate its RTL implementation on FPGAs. By using Physical Random Functions, we propose a new way of reliably protecting and sharing secrets that is more(More)
In this thesis, a high level programming model for the AEGIS secure processor is designed and implemented. The AEGIS processor enables developers to create trusted systems, while only needing to trust the AEGIS processor. In order for developers to utilize the processor, there was a need for high level access to the low level AEGIS constructs. There was(More)
In this thesis, a high level programming model for the AEGIS secure processor is designed and implemented. The AEGIS processor enables developers to create trusted systems, while only needing to trust the AEGIS processor. In order for developers to utilize the processor, there was a need for high level access to the low level AEGIS constructs. There was(More)
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