Ioanna Theologitou

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This paper presents an efficient architecture for system level verification of multiprocessor SoCs. We introduce an architecture based on the re-use of existing structures, such as on-chip buses, for core verification and protocol execution monitoring. The proposed scheme is best applicable to SoCs for telecommunication applications, which are built upon a(More)
In this paper we present the experience gained from the design and verification of a complex network processor. The PRO3 processor1 can operate in either ATM or IP based multiprotocol networking environments, supporting link rates up to 2.4 Gbps. We describe the methodology followed during the verification process, from specifications to silicon prototype(More)
In multimedia applications, the stringent requirements for balancing transmission capacity, flexible service provisioning and cost reduction lead the manufactures to provide highly integrated System-on Chip (SoC) solutions. This paper analyzes the application of high-bandwidth-networking SoCs to improve on the cost efficiency of multimedia service(More)
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