Intaik Park

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&A TRANSITION FAULT model typically guides test pattern generation to cover defects that cause late signal transitions. 1 Such a delay test requires a two-pattern test: The first pattern initializes a node signal value. The second pattern causes this value to switch to the opposite value and sensitize the transition to an observable output. These two events(More)
Delay testing is a technique to determine if a chip will function correctly at a specified frequency. If a chip passes delay tests, it will presumably function at the specified frequency in the field. This paper presents experimental results that show how chips can pass very thorough delay tests and still fail in the field. It is shown that some chips(More)
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