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- Jaeha Kung, Inhak Han, Sachin S. Sapatnekar, Youngsoo Shin
- 2011 48th ACM/EDAC/IEEE Design Automation…
- 2011

A floorplanning has a potential to reduce chip temperature due to the conductive nature of heat. If floorplan optimization, which is usually based on simulated annealing, is employed to reduce temperature, its evaluation should be done extremely fast with high accuracy. A new thermal index, named thermal signature, is proposed. It approximates the… (More)

- Sangmin Kim, Inhak Han, Seungwhun Paik, Youngsoo Shin
- 16th Asia and South Pacific Design Automation…
- 2011

A pulsed-latch is an ideal sequencing element for low-power ASIC designs due to its smaller capacitance and simple timing model. Clock gating of pulsed-latch circuits can be realized by gating a pulse generator (or pulser), which we call pulser gating. The problem of pulser gating synthesis is formulated for the first time. Given a gate-level netlist with… (More)

- Inhak Han, Youngsoo Shin
- IEEE Trans. VLSI Syst.
- 2014

- Inhak Han, Daijoon Hyun, Youngsoo Shin
- 2016 21st Asia and South Pacific Design…
- 2016

Buffer insertion to remove hold violations at multiple process corners is addressed for the first time. The problem is formulated as integer linear programming (ILP); it is combined with circuit partitioning heuristic so that larger circuits can also be handled. A heuristic buffer insertion algorithm is then proposed and compared to ILP, which demonstrates… (More)

- Inhak Han, Jonggyu Kim, Joonhwan Yi, Youngsoo Shin
- ICICDT
- 2016

- Inhak Han, Youngsoo Shin
- ICICDT
- 2012

- Seungwhun Paik, Inhak Han, Sangmin Kim, Youngsoo Shin
- IEEE Transactions on Computer-Aided Design of…
- 2012

Pulsed-latch circuits, in which latches are triggered by a short pulse, can reduce power consumption as well as increasing performance; and they can largely be designed using conventional computer-aided design tools. We explore the automatic synthesis of clock-gating logic for pulsed-latch circuits in which gating is implemented by enabling and disabling… (More)

- Inhak Han, Lee-eun Yu, Youngsoo Shin
- 2010 IEEE International Conference on Integrated…
- 2010

Monte Carlo (MC) method is convenient and robust to estimate timing yield of circuits under the influence of process variations. The important question in MC method is the number of samples while we assure a desired accuracy of yield estimate, which is often addressed using a rule of thumb. Minimum number of samples can be estimated via approximation by a… (More)

- Inhak Han, Youngsoo Shin
- ICICDT
- 2013

Dual edge-triggered flip-flop (DETFF) captures data at both clock edges. We observe that conventional sequential circuit that contains single edge-triggered flip-flops (SETFFs) can be simplified by identifying pairs of combinational subcircuits that are structurally identical, removing one subcircuit of each pair, and providing input data twice by using… (More)

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