Indrajit Chakrabarti

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This paper proposes a low-power, high-speed architecture of a reconfigurable root-raised cosine (RRC) filter which serves as a major component of a digital up converter (DUC). The proposed RRC filter can be reconfigured at any time to suit one of three different interpolation factors and one of two different roll-off factors pertaining to various modern(More)
H.264, which is the most advanced video compression standard till date, includes novel algorithms for quantization and inverse quantization processes. In this paper, a new hardware architecture exclusively based on combinational logic is proposed for the quantizer and inverse quantizer blocks for real-time video processing. Implemented in Xilinx14.1,(More)
In this paper an FPGA implementation of a high performance programmable digital FM modem has been done for targeting towards the Software Defined Radio (SDR) application. The proposed design consists of the reprogrammable, area optimized and low-power features. The modulator and demodulator contain a compressed direct digital synthesizer (DDS) for(More)
Considerable research has taken place in recent times in the area of parameterization of software defined radio (SDR) architecture. Parameterization decreases the size of the software to be downloaded and also limits the hardware reconfiguration time. The present paper is based on the design and development of a programmable baseband modulator that perform(More)
Most of the area occupied in the design of FIR filter is the multiplier. The low power and area architecture of pulse shaping FIR filter for digital up converter was designed. In the existing system, the two bit binary common sub-expression based binary common sub-expression elimination algorithm and shift and add method was used to generate the partial(More)