Indrajit Chakrabarti

Learn More
This paper proposes new low-power, high-speed architecture and its FPGA validation of a multi-tap reconfigurable RRC FIR filter, one of the major components in DUC. The proposed RRC filter can support three different interpolation factors along with two different roll-off factors mostly used in the present days wireless communication standards. The design(More)
Considerable research has taken place in recent times in the area of parameterization of software defined radio (SDR) architecture. Parameterization decreases the size of the software to be downloaded and also limits the hardware reconfiguration time. The present paper is based on the design and development of a programmable baseband modulator that perform(More)
Most of the area occupied in the design of FIR filter is the multiplier. The low power and area architecture of pulse shaping FIR filter for digital up converter was designed. In the existing system, the two bit binary common sub-expression based binary common sub-expression elimination algorithm and shift and add method was used to generate the partial(More)