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This paper proposes new low-power, high-speed architecture and its FPGA validation of a multi-tap reconfigurable RRC FIR filter, one of the major components in DUC. The proposed RRC filter can support three different interpolation factors along with two different roll-off factors mostly used in the present days wireless communication standards. The design(More)
Considerable research has taken place in recent times in the area of parameterization of software defined radio (SDR) architecture. Parameterization decreases the size of the software to be downloaded and also limits the hardware reconfiguration time. The present paper is based on the design and development of a programmable baseband modulator that perform(More)
— This paper introduces a novel energy efficient architecture for a turbo decoder using quadratic permutation polynomial (QPP) interleaver The Add Compare Select Offset (ACSO) unit of the maximum a posteriori probability (MAP) decoder, has been pipelined to a depth of four to reduce the critical path delay and increase the operating clock frequency and(More)