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A higher performance DRAM is required by the market due to the increasing of bandwidth of networks and the rise of high-capacity multimedia content. DDR4 SDRAM is the next-generation memory that meets these demands in computing and server systems. In comparison with current DDR3 memory, the major changes are supply voltage reduction to 1.2V, pseudo open(More)
For the demand of sever systems with high performance, high density and low power consumption, 3-D DDR4 SDRAM with TSVs was developed. In order to achieve higher data rate at lower voltage in comparison with precedent DDR3 SDRAM with TSVs, the placements of TSVs have been optimized without the penalty of chip size and the calibration method for reducing(More)
This paper describes DLL architecture and ZQ calibration method for 30nm 1.2V 4Gb 3.2Gb/s/pin DDR4 SDRAM. Proposed DLL consists of one DLL with CML DCDL and another DLL with CMOS DCDL which tracks first one for low jitter and low power characteristics. Quantization error minimized (QEM) ZQ calibration is proposed for better signal integrity and yield(More)
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