Ilgweon Kang

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Testability of ECO logic is currently a significant bottleneck in the SOC implementation flow. Front-end designers sometimes require large functional ECOs close to scheduled tapeout dates or for later design revisions. To avoid loss of test coverage, ECO flip-flops must be added into existing scan chains with minimal increase to test time and minimal impact(More)
Built-in self-test (BIST) is a well-known design technique in which part of a circuit is used to test the circuit itself. BIST plays an important role for embedded memories, which do not have pins or pads exposed toward the periphery of the chip for testing with automatic test equipment. With the rapidly increasing number of embedded memories in modern SOCs(More)
We propose a flat, analytic, mixed-size placement algorithm ePlace-3D for three-dimension integrated circuits (3D-ICs) using nonlinear optimization. Our contributions are (1) electrostatics based 3D density function with globally uniform smoothness (2) 3D numerical solution with improved spectral formulation (3) 3D nonlinear pre-conditioner for convergence(More)
We propose an efficient algorithmic framework for time-domain circuit simulation using exponential integrators. This work addresses several critical issues exposed by previous matrix exponential based circuit simulation research, and makes it capable of simulating stiff nonlinear circuit system at a large scale. In this framework, the system's nonlinearity(More)
Data/algorithmic representations of 3D floorplans for integrated circuits is an essential problem in the study of 3D VLSI circuits. Given a fixed number of rectangular blocks and their volume, 3D floorplan representations describe their orientations and positions relative to the origin in a three dimensional space. In our study, we 1). present and analyze a(More)
We design an algorithmic framework using matrix exponentials for time-domain simulation of power delivery network (PDN). Our framework can reuse factorized matrices to simulate the large-scale linear PDN system with variable stepsizes. In contrast, current conventional PDN simulation solvers have to use fixed step-size approach in order to reuse factorized(More)
The key words of DRAM technology are low cost and mass productivity. One of the best ways to get this goal continues to improve the ability for manufactures to shrink their technology, essentially getting more device chips per wafer through process scaling. With the growing in memory density and the shrinking into design rule, neighborhood pattern sensitive(More)
This paper presents Fault Tolerant Carry Select Adder (FT-CSA), most widely used type of adder, based on the self checking scheme with modular architecture. The error recovery capability is derived using generic input/output combination of carry select adder with predetermined fault and error set. The experimental results show that proposed FT-CSA has(More)
Innovations and advancements on physical design (PD) in the past half century significantly contribute to the progresses of modern VLSI designs. While ``Moore's Law'' and ``Dennard Scaling'' have become slowing down recently, physical design society encountered a set of challenges and opportunities. This article is presented at the event of the Life Time(More)
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