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This paper describes a novel processor architecture, the prioritized SMT architecture with the IPC control method, to guarantee the execution time of real-time threads. Based on priority set by a real-time scheduler, all hardware resources including cache systems, fetch, issue, and execution units, are controlled, so that our processor can execute multiple(More)
GPU and FPGA-based clouds have already demonstrated the promise of accelerating computing-intensive workloads with greatly improved power and performance. In this paper, we examine the design of ASIC Clouds, which are purpose-built datacenters comprised of large arrays of ASIC accelerators, whose purpose is to optimize the total cost of ownership (TCO) of(More)
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