Ihsan J. Djomehri

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It has been shown that the double-gate MOSFET can provide high current drive and good electrostatic integrity at gate lengths of 20-30 nm. The top and bottom gates should be perfectly aligned to maximize current drive and to avoid introducing a varying overlap capacitance between the bottom gate and source/drain regions. Perfect alignment is best achieved(More)
Direct quantitative 2-D characterization of sub-50 nm MOSFETs continues to be elusive. This research develops a comprehensive indirect inverse modeling technique for extracting 2-D device topology using combined log(I)-V and C-V data. An optimization loop minimizes the error between a broad range of simulated and measured electrical characteristics by(More)
As MOSFET dimensions are reduced to the sub-100 nm level, the electrical performance is critically dependent on the two-dimensional topology and concentrations of dopants in the semiconductor. In order to characterize, predict, and control the device topology, and hence the device behavior, it is essential to have a method of obtaining an accurate(More)
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