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This paper presents a methodology for determining the probability of structural failures for VLSI circuits. An analytically based approach is used to perform simulations accurately and efficiently. This approach considers the specific IC layout and accounts for most of the fault mechanisms caused by global geometrical variations and local defects. A(More)
This paper presents a general methodology for designing optimal test structures and their applications to characterize the process fluctuations inherent in IC manufacturing. A set of test structures, including a novel test structure, is presented in which each test structure parameter is sensitive to a minimal number of process parameters. The procedure for(More)
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