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Throughput, power consumption, signal integrity, pin count and routing complexity are all increasingly important interconnect issues that the system designer must deal with. Recent advances in integrated optical devices may deliver alternative interconnect solutions enabling drastically enhanced performance. This paper begins by outlining some of the more(More)
This article presents IDEA1, a SystemC-based system-level design and simulation framework for WSNs. It allows the performance evaluation (e.g., packet delivery rate, transmission latency and energy consumption) at high level, but with elaborate models of the hardware and software of sensor nodes. Many hardware components are modeled and the IEEE 802.15.4(More)
In the near future, Multi-Processor Systems-on-Chip (MPSoC) will become the main thrust driving the evolution of integrated circuits. MPSoCs introduce new challenges, mainly due to growing communication through their interconnect structure. Current electrical interconnects will face hard challenges to overcome such data flows. Integrated optical(More)
— State-of-the-art System-on-Chip (SoC) consists of hundreds of processing elements, while trends in design of the next generation of SoC point to integration of thousand of processing elements, requiring high performance interconnect for high throughput communications. Optical on-chip interconnects are currently considered as one of the most promising(More)
In this paper, we present a tool to analyse photonic devices that can be used to realize basic building blocks of an optical network-on-chip (ONoC). Co-design between electrical tools and optical tools is possible. The VHDL-AMS language has been used to implement behavioral models of photonic devices. For low-level simulation, a gateway between an optical(More)
— 1 Optical network on chip (ONoC) architectures are emerging as potential contenders to solve congestion and latency issues in future computing architectures. In this work, we examine how a scalable and fully connected ONoC topology can be reduced to fit specific connectivity requirements in MPSoCs and heterogeneous SoCs. Through such techniques, it is(More)
—Integrated optical interconnect has been identified by the ITRS as a potential solution to overcome predicted interconnect limitations in future systems-on-chip. However, the multiphysics nature of the design problem and the lack of a mature integrated photonic technology have contributed to severe difficulties in assessing its suitability. This paper(More)
The evolution of integrated circuit technology is causing system designs to move towards communication-based architectures. However, metallic interconnect networks (networks-on-chip) can be very costly in terms of power and silicon area and can thus become a bottleneck in system on chip design. Integrated optical networks-on-chip could be good candidates to(More)