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— Recently, various multibit noise-shaping digital-to-analog converters (DAC's) have been proposed that use digital signal processing techniques to cause the DAC noise arising from analog component mismatches to be spectrally shaped. Such DAC's have the potential to significantly increase the present precision limits of 16 data converters by eliminating the(More)
—Pipelined analog-to-digital converters (ADCs) are sensitive to distortion introduced by the residue amplifiers in their first few stages. Unfortunately, residue amplifier distortion tends to be inversely related to power consumption in practice, so the residue amplifiers usually are the dominant consumers of power in high-resolution pipelined ADCs. This(More)
Phase-noise cancellation makes it possible to greatly widen the loop bandwidth of a ΔΣ fractional-N PLL without the massive increase in phase noise that would otherwise be caused by the ΔΣ quantization noise [1-4]. This allows the loop filter to be integrated on-chip, reduces sensitivity of the VCO to pulling and noise, better attenuates in-band VCO noise,(More)
—Theoretical sufficient conditions are presented that ensure that the quantization noise from every constituent digital delta–sigma (16) modulator in a multistage digital 16 modu-lator is asymptotically white and uncorrelated with the input. The conditions also determine if spectral shape can be imparted to the dither's contribution to the power spectral(More)
A digitally background calibrated ring oscillator ADC ΔΣ modulator is presented that consists mostly of digital circuitry. It does not contain analog integrators, feedback DACs, comparators, or reference voltages, and does not require a low-jitter clock. Unlike conventional ΔΣ modulators, its performance depends mainly on the speed of its digital circuitry,(More)
—This paper presents a reconfigurable continuous-time delta-sigma modulator for analog-to-digital conversion that consists mostly of digital circuitry. It is a voltage-controlled ring oscillator based design with new digital background calibration and self-cancelling dither techniques applied to enhance performance. Unlike conventional delta-sigma(More)
A pipelined ADC is presented with 2 fully integrated digital background calibration techniques: harmonic distortion correction (HDC) to compensate for residue amplifier gain error and nonlinearity, and DAC noise cancellation (DNC) to compensate for DAC capacitor mismatches [1,2]. It is the first IC implementation of HDC, and the results demonstrate that HDC(More)
A major problem with fractional-N PLLs is that their phase noise contains fractional spurs, i.e., spurious tones at multiples of f ref times the fractional part of f out /f ref , where f out and f ref are the PLL output and reference frequencies, respectively. In prior fractional-N PLLs fractional spurs within the loop BW tend to be large, typically well(More)
—An analysis of the quantization noise introduced by a widely-used class of single-quantizer digital delta–sigma (16) modulators with low-level, 1-bit dither is presented. Necessary and sufficient conditions are derived that ensure, in an asymptotic sense, various ensemble statistical properties of the quantization noise such as uniformity and independence(More)