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Recently, various multibit noise-shaping digital-toanalog converters (DAC’s) have been proposed that use digital signal processing techniques to cause the DAC noise arising from analog component mismatches to be spectrally shaped. Such DAC’s have the potential to significantly increase the present precision limits of data converters by eliminating the need(More)
This paper presents and analyzes a new dynamic element matching technique for low-harmonic distortion digitalto-analog conversion. The benefit of this technique over the prior art is a significantly reduced hardware complexity with no reduction in performance. It is particularly appropriate for applications such as direct digital synthesis (DDS) in wireless(More)
Pipelined analog-to-digital converters (ADCs) are sensitive to distortion introduced by the residue amplifiers in their first few stages. Unfortunately, residue amplifier distortion tends to be inversely related to power consumption in practice, so the residue amplifiers usually are the dominant consumers of power in high-resolution pipelined ADCs. This(More)
Phase-noise cancellation makes it possible to greatly widen the loop bandwidth of a ΔΣ fractional-N PLL without the massive increase in phase noise that would otherwise be caused by the ΔΣ quantization noise [1-4]. This allows the loop filter to be integrated on-chip, reduces sensitivity of the VCO to pulling and noise, better attenuates in-band VCO noise,(More)
This paper presents a reconfigurable continuous-time delta-sigma modulator for analog-to-digital conversion that consists mostly of digital circuitry. It is a voltage-controlled ring oscillator based design with new digital background calibration and self-cancelling dither techniques applied to enhance performance. Unlike conventional delta-sigma(More)
A pipelined ADC is presented with 2 fully integrated digital background calibration techniques: harmonic distortion correction (HDC) to compensate for residue amplifier gain error and nonlinearity, and DAC noise cancellation (DNC) to compensate for DAC capacitor mismatches [1,2]. It is the first IC implementation of HDC, and the results demonstrate that HDC(More)
A major problem with fractional-N PLLs is that their phase noise contains fractional spurs, i.e., spurious tones at multiples of fref times the fractional part of fout/fref, where fout and fref are the PLL output and reference frequencies, respectively. In prior fractionalN PLLs fractional spurs within the loop BW tend to be large, typically well above(More)
Theoretical sufficient conditions are presented that ensure that the quantization noise from every constituent digital delta–sigma ( ) modulator in a multistage digital modulator is asymptotically white and uncorrelated with the input. The conditions also determine if spectral shape can be imparted to the dither’s contribution to the power spectral density(More)
This paper presents a second-generation mostly-digital background-calibrated oversampling ADC based on voltagecontrolled ring oscillators (VCROs). Its performance is in line with the best modulator ADCs published to date, but it occupies much less circuit area, is reconfigurable, and consists mainly of digital circuitry. Enhancements relative to the(More)