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—Pipelined analog-to-digital converters (ADCs) are sensitive to distortion introduced by the residue amplifiers in their first few stages. Unfortunately, residue amplifier distortion tends to be inversely related to power consumption in practice, so the residue amplifiers usually are the dominant consumers of power in high-resolution pipelined ADCs. This(More)
—This paper presents a reconfigurable continuous-time delta-sigma modulator for analog-to-digital conversion that consists mostly of digital circuitry. It is a voltage-controlled ring oscillator based design with new digital background calibration and self-cancelling dither techniques applied to enhance performance. Unlike conventional delta-sigma(More)
—An analysis of the quantization noise introduced by a widely-used class of single-quantizer digital delta–sigma (16) modulators with low-level, 1-bit dither is presented. Necessary and sufficient conditions are derived that ensure, in an asymptotic sense, various ensemble statistical properties of the quantization noise such as uniformity and independence(More)
—Theoretical sufficient conditions are presented that ensure that the quantization noise from every constituent digital delta–sigma (16) modulator in a multistage digital 16 modu-lator is asymptotically white and uncorrelated with the input. The conditions also determine if spectral shape can be imparted to the dither's contribution to the power spectral(More)
A pipelined ADC is presented with 2 fully integrated digital background calibration techniques: harmonic distortion correction (HDC) to compensate for residue amplifier gain error and nonlinearity, and DAC noise cancellation (DNC) to compensate for DAC capacitor mismatches [1,2]. It is the first IC implementation of HDC, and the results demonstrate that HDC(More)
—A fast-settling adaptive calibration technique is presented that makes phase noise cancelling 16 fractional-PLLs practical for the low reference frequencies commonly used in wireless communication systems. The technique is demonstrated as an enabling component of a 2.4 GHz ISM band CMOS PLL IC with a 730 kHz bandwidth, a 12 MHz reference, and an on-chip(More)
—Dynamic element matching (DEM) is widely used in multibit digital–analog converters (DACs) to prevent mis-matches among nominally identical components from introducing nonlinear distortion. It has long been used as a performance-enabling technique in delta-sigma data converters which require low-resolution but high-linearity DACs. More recently, segmented(More)
—This paper demonstrates that spurious tones in the output of a fractional-N PLL can be reduced by replacing the 16 modulator with a new type of digital quantizer and adding a charge pump offset combined with a sampled loop filter. It describes the underlying mechanisms of the spurious tones, proposes techniques that mitigate the effects of the mechanisms,(More)