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An ultra low-power processor for sensor networks
TLDR
We present a novel processor architecture designed specifically for use in low-power wireless sensor-network nodes. Expand
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BitSNAP: dynamic significance compression for a low-energy sensor network asynchronous processor
TLDR
We present a novel asynchronous processor architecture called BitSNAP that utilizes bit-serial datapaths with dynamic significance compression to yield extremely low-energy consumption. Expand
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SNAP: a Sensor-Network Asynchronous Processor
TLDR
We present a Sensor-Network Asynchronous Processor (SNAP), which we have designed to be both a processor core for a sensor-network node and a component of a chip multiprocessor, the Network on a Chip (NoC), which will execute a novel Sensor-network simulator. Expand
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Network on a chip: modeling wireless networks with asynchronous VLSI
TLDR
We introduce the notion of a network on a chip: a programmable asynchronous VLSI architecture for fast and efficient simulation of wireless networks. Expand
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An event-synchronization protocol for parallel simulation of large-scale wireless networks
TLDR
We present a new conservative event-synchronization protocol, a time-based synchronization, for parallel discrete-event simulation of mobile ad hoc wireless networks. Expand
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Energy-Efficient Pipelines
TLDR
We show that pipelines optimized for the E energy-time metric may need fewer buffer stages and we give bounds when such stages can be removed. Expand
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