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Benchmarking of Beyond-CMOS Exploratory Devices for Logic Integrated Circuits
A new benchmarking of beyond-CMOS exploratory devices for logic integrated circuits is presented. It includes new devices with ferroelectric, straintronic, and orbitronic computational state…
Overview of Beyond-CMOS Devices and a Uniform Methodology for Their Benchmarking
Structural and operational principles of multiple logic devices under study within the NRI to carry the development of integrated circuits beyond the complementary metal-oxide-semiconductor (CMOS) roadmap are described, and theories used for benchmarking these devices are overviewed.
Scalable energy-efficient magnetoelectric spin–orbit logic
A scalable spintronic logic device operating via spin–orbit transduction and magnetoelectric switching and using advanced quantum materials shows non-volatility and improved performance and energy efficiency compared with CMOS devices.
Modeling and Design of Spintronic Integrated Circuits
- S. Manipatruni, D. Nikonov, I. Young
- PhysicsIEEE Transactions on Circuits and Systems I…
- 21 November 2012
A theoretical and a numerical formalism for analysis and design of spintronic integrated circuits (SPINICs) and an extension to the modified nodal analysis technique for the analysis of spin circuits based on the recently developed spin conduction matrices are proposed.
Optical I/O technology for tera-scale computing
- I. Young, E. Mohammed, P. Chang
- Computer ScienceIEEE International Solid-State Circuits…
- 22 December 2009
Results are described for both near and long-term chip-to-chip optical interconnect architectures that replace electrical interconnect between chips with its terahertz bandwidth, low loss, and low cross-talk.
Tunnel Field-Effect Transistors: Prospects and Challenges
The tunnel field-effect transistor (TFET) is considered a future transistor option due to its steep-slope prospects and the resulting advantages in operating at low supply voltage (VDD). In this…
Energy-delay performance of giant spin Hall effect switching for dense magnetic memory
We show that the giant spin Hall effect (GSHE) magnetoresistive random access memory (MRAM) can enable better energy delay and voltage performance than MTJ spin torque devices at 10–30 nm scaled…
Design of Low Voltage Tunneling-FET Logic Circuits Considering Asymmetric Conduction Characteristics
- D. Morris, U. Avci, R. Rios, I. Young
- EngineeringIEEE Journal on Emerging and Selected Topics in…
- 17 October 2014
It is revealed that relatively large voltages can be bootstrapped within digital TFET circuits, which is unique to TFETs and may have significant speed and reliability impacts.
Uniform methodology for benchmarking beyond-CMOS logic devices
A consistent methodology for benchmarking beyond CMOS logic devices was developed to guide the research directions and two promising devices - tunneling FET and spin wave devices - are identified.
Understanding the feasibility of scaled III–V TFET for logic by bridging atomistic simulations and experimental results
- U. Avci, S. Hasan, D. Nikonov, R. Rios, K. Kuhn, I. Young
- PhysicsSymposium on VLSI Technology (VLSIT)
- 12 June 2012
A detailed comparison between III-V TFET's experimental characteristics and atomistic quantum mechanical predictions is reported, suggesting that the experimental devices are without significant unknown effects or defects, and the atomistic simulations have good predictability.