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A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation
  • K. Tiri, I. Verbauwhede
  • Computer Science
  • Proceedings Design, Automation and Test in Europe…
  • 16 February 2004
This paper describes a novel design methodology to implement a secure DPA resistant crypto processor. The methodology is suitable for integration in a common automated standard cell ASIC or FPGAExpand
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A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards
To protect security devices such as smart cards against power attacks, we propose a dynamic and differential CMOS logic style. The logic operates with a power consumption independent of both theExpand
  • 513
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Physically Unclonable Functions: A Study on the State of the Art and Future Research Directions
The idea of using intrinsic random physical features to identify objects, systems, and people is not new. Fingerprint identification of humans dates at least back to the nineteenth century [21] andExpand
  • 352
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spongent: A Lightweight Hash Function
This paper proposes spongent - a family of lightweight hash functions with hash sizes of 88 (for preimage resistance only), 128, 160, 224, and 256 bits based on a sponge construction instantiatedExpand
  • 246
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Compact Ring-LWE Cryptoprocessor
In this paper we propose an efficient and compact processor for a ring-LWE based encryption scheme. We present three optimizations for the Number Theoretic Transform NTT used for polynomialExpand
  • 152
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PUFKY: A Fully Functional PUF-Based Cryptographic Key Generator
We present PUFKY: a practical and modular design for a cryptographic key generator based on a Physically Unclonable Function (PUF). A fully functional reference implementation is developed andExpand
  • 223
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A 21.54 Gbits/s fully pipelined AES processor on FPGA
This paper presents the architecture of a fully pipelined AES encryption processor on a single chip FPGA. By using loop unrolling and inner-round and outer-round pipelining techniques, a maximumExpand
  • 258
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A soft decision helper data algorithm for SRAM PUFs
In this paper we propose the idea of using soft decision information in helper data algorithms (HDA). We derive and verify a distribution for the responses of SRAM-based physically unclonableExpand
  • 148
  • 24
Chaskey: An Efficient MAC Algorithm for 32-bit Microcontrollers
We propose Chaskey: a very efficient Message Authentication Code (MAC) algorithm for 32-bit microcontrollers. It is intended for applications that require 128-bit security, yet cannot implementExpand
  • 119
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Securing Encryption Algorithms against DPA at the Logic Level: Next Generation Smart Card Technology
This paper describes a design method to secure encryption algorithms against Differential Power Analysis at the logic level. The method employs logic gates with a power consumption, which isExpand
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