• Publications
  • Influence
A head-mounted three dimensional display
  • I. Sutherland
  • Computer Science
  • AFIPS '68 (Fall, part I)
  • 9 December 1968
The fundamental idea behind the three-dimensional display is to present the user with a perspective image which changes as he moves, and this display depends heavily on this "kinetic depth effect". Expand
The pipeline processor is a common paradigm for very high speed computing machinery that can be found in graphics processors, in signal processing devices, in integrated circuit components for doing arithmetic, and in the instruction interpretation units and arithmetic operations of general purpose computing machinery. Expand
Sketchpad: a man-machine graphical communication system
The Sketchpad system makes it possible for a man and a computer to converse rapidly through the medium of line drawings, and opens up a new area of man-machine communication. Expand
The Ultimate Display
The authors live in a physical world whose properties they have come to know well through long familiarity but lack corresponding familiarity with the forces on charged particles, forces in non-uniform fields, the effects of nonprojective geometric transformations, and high-inertia, low friction motion. Expand
GasP: a minimal FIFO control
The GasP family of asynchronous circuits provides controls for simple pipelines, for branching and joining pipelines, with assurance of uniform gate delays permits use of self-resetting logic forms that have very low logical effort. Expand
Logical effort: designing for speed on the back of an envelope
Outline t Introduction t Delay in a Logic Gate t Multi-stage Logic Networks t Choosing the Best Number of Stages t Example t Summary
A Characterization of Ten Hidden-Surface Algorithms
The paper shows that the order of sorting and the types of sorting used form differences among the existing hidden-surface algorithms. Expand
A futures market in computer time
An auction method is described for allocating computer time that allows the price of computer time to fluctuate with the demand and the relative priority of users to be controlled so that moreExpand
The counterflow pipeline processor architecture
The CFPP architecture and a proposal for an asynchronous implementation are presented and the architecture seeks geometric regularity in processor chip layout, purely local control to avoid performance limitations of complex global pipeline stall signals, and simplicity that might lead to provably correct processor designs. Expand