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A CMOS charge pump for low voltage operation
TLDR
This paper proposes a low-voltage, high performance charge pump circuit suitable for implementation in standard CMOS technologies. Expand
  • 86
  • 4
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A single-chip digitally calibrated 5.15-5.825-GHz 0.18-/spl mu/m CMOS transceiver for 802.11a wireless LAN
TLDR
The drive for cost reduction has led to the use of CMOS technology in the implementation of highly integrated radios. Expand
  • 108
  • 3
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Differential CMOS edge-triggered flip-flop based on clock racing
A differential CMOS edge-triggered flip-flop is proposed that employs a pair of cross-coupled inverters, providing fully static operation. The edge-triggering operation is achieved by a narrow pulse,Expand
  • 11
  • 3
A single-chip, 5.15GHz-5.35GHz, 2.4GHz-2.5GHz, 0.18/spl mu/m CMOS RF transceiver for 802.11a/b/g wireless LAN
TLDR
A dual band, 5.15GHz-5.5GHz, zero-IF transceiver is fabricated on a 0.18/spl mu/m CMOS process. Expand
  • 13
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Fast 1V bootstrapped inverter suitable for standard CMOS technologies
The authors propose a novel low-voltage bootstrapped inverter, designed in a standard high VT 0.35µm CMOS technology. To enhance the switching speed of a CMOS inverter at low-voltage operation, anExpand
  • 5
  • 1
A dual-band 5.15-5.35-GHz, 2.4-2.5-GHz 0.18-/spl mu/m CMOS transceiver for 802.11a/b/g wireless LAN
TLDR
A single-chip dual-band 5.5-GHz zero-IF transceiver for IEEE 802.11a/b/g WLAN systems is fabricated on a 0.18-/spl mu/m CMOS technology. Expand
  • 60
Charge Pump Circuits for Low-voltage Applications
TLDR
In this paper, a low-voltage, high performance charge pump circuit, suitable for implementation in standard CMOS technologies is proposed, based on cascading several crossconnected NMOS voltage doubler stages. Expand
  • 8
  • PDF
Dynamic back bias CMOS driver for low-voltage applications
A high performance CMOS driver scheme for low-voltage applications is proposed. The threshold voltage of the MOS devices is electrically controlled in order to achieve high-speed operation during theExpand
  • 7
A CMOS differential logic for low-power and high-speed applications
TLDR
A new logic family called Charge-sharing at precharge differential logic (CSPDL) is proposed. Expand
  • 3
A high speed low power CMOS clock driver using charge recycling technique
TLDR
This paper presents an Improved Power-Delay Product (PDP) CMOS clock driver based on the charge recycling technique. Expand
  • 4
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