• Publications
  • Influence
Hardware-software codesign of accurate, multiplier-free Deep Neural Networks
We propose a novel approach to map floating-point based DNNs to 8-bit dynamic fixed-point networks with integer power-of-two weights with no change in network architecture. Expand
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Energy Implications of Transactional Memory for Embedded Architectures
Roughly ninety percent of all microprocessorsmanufactured in any one year are intended for embedded devices such as cameras, cell-phones, or machine controllers. We evaluate the energy-efficiency andExpand
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Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures
It is our pleasure to present the following program for Nanoarch 2010. Expand
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Power and Performance Tradeoffs using Various Cache Configurations
In this paper, we will propose several different data and instruction cache configurations and analyze their power and performance implications on the processor. Expand
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An ADD-Based Symbolic Analysis of Leakage Current in CMOS Circuits
In this paper we target the leakage problem in CMOS circuits symbolically using Algebraic Decision Diagrams (ADDs). Expand
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Energy-efficient and Sustainable Computing across the Hardware/Software Stack
  • I. Bahar
  • Computer Science
  • IGSC
  • 1 October 2019
In this talk, I will present techniques—past and present—across the HW/SW stack, for energy-efficient and reliable computing. Expand
Flexibl eDat aAllocatio nfo rScratch-pa dMemorie st oReduc eNBTI Effects
Negative Bias Temperature Instability (NBTI) is a major reliability issue in nanoscale VLSI sys- tems. Previous work has shown how the exploitation of conventional optimization techniques can reduceExpand
NSF Workshop Report : Architectures for Silicon Nanoelectronics and Beyond 2
As semiconductor technology continues it relentless push to smaller geometry and as new emerging devices become feasible, the microelectronics and computer industry will be facing significantExpand
A Comparison of Software Code Reordering and
We compare the effectiveness of compiler-based code-placement algorithms to hardwarebased schemes using a full simulation model of an out-oforder, 4-way issue processor. Expand
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