I. Naritake

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We present an ultra-high-performance 0.13-/spl mu/m embedded DRAM technology, which improves transistor performance in both logic devices and DRAM cells. Simulation results indicate that the typical random access cycle of a 16-Mbit DRAM core exceeds 570 MHz. The full-metal DRAM structure having a newly developed TiN/HfO/sub 2//TiN/W capacitor minimizes the(More)
Bit-cost reduction is one of the most serious issues for file application DRAMs. Chip size reduction or density increase has been an effective solution. Lithographic technology has permitted this density increase through 70% reduction in the minimum design rule for each subsequent DRAM generation. However, for further density increase, another memory cell(More)
This paper describes three circuit technologies that have been developed for high-speed large-bandwidth on-chip DRAM secondary caches. They include a redundancy-array advanced activation scheme, a bus-assignment-exchangeable selector scheme and an address-zero access refresh scheme. By using these circuit technologies and new small subarray structures, a(More)
The most important advantage of on-chip DRAMs is high bandwidth between a DRAM and a processor. Many circuit technologies are used to enlarge the bandwidth. For example, sense amplifier data are extracted by a number of data-lines parallel to the bit-lines in some DRAMs. Even if these circuits are used, random accesses substantially degrade the bandwidth(More)
We have developed a 0.13 /spl mu/m embedded DRAM technology, which targets high-speed and low-voltage operation, with logic performance fully compatible with 0.13 /spl mu/m pure logic. Parasitics (resistance, capacitance) of the DRAM macro limit its performances due to RC delay and IR drop. The parasitics of the new DRAM have been successfully minimized by(More)
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