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The 3-D integrated dynamic random-access memory (DRAM) structure with a processor is being widely studied due to advantages, such as a large band-width and data communication power reduction. In these structures, the massive heat generation of the processor results in a high operating temperature and a high refresh rate of the DRAM. Thus, in the 3-D DRAM(More)
Three-dimensional integrated circuits (3-D ICs) are considered to meet the performance needs of future ICs. The core components of 3-D ICs are through-silicon vias (TSVs), which should pass appropriate prebond and post-bond tests in 3-D IC fabrication processes. The test inputs must be injected into the TSVs, and the test results must be extracted. This(More)
A new 3-D fuse architecture is proposed to improve the yield of 3-D memories. Because the 2-D memories are stacked to form a 3-D memory, the repair status of the prebond is kept as the good status. However, if faults occur in the postbond on the same cells which were repaired in the prebond, they must be identified and repaired because they cannot be(More)
Ensuring lifetime reliability of microprocessors has become more critical. Continuous scaling and increasing temperatures due to growing power density are threatening lifetime reliability. Negative bias temperature instability (NBTI) has been known for decades, but its impact has been insignificant compared to other factors. Aggressive scaling, however,(More)
The exponential advance in semiconductor manufacturing technology is bringing heavy increase not only in power consumption but in test data volume as well. Moreover, power consumption in test mode is much higher than that in the functional operation mode. In this paper, a low power scan bypass technique is proposed to reduce both the test data volume and(More)
Power consumption during scan-based testing can be higher than that of normal mode opeartions, which can cause yield loss and degradation of reliability. This paper proposes a scan cell reordering algorithm to reduce the test power consumption during scan-based testing. The proposed algorithm considers both shift-out operations and shift-in operations. A(More)
Stacking core layers is emerging as an alternative for future high performance computing, but thermal problems have to be tackled first. When adaptive voltage scaling is adopted to hide the growing variation in the performance of cores, as a result, heat generation of each core varies. By exploiting the static thermal characteristics, the efficiency of(More)