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The phase-change random access memory (PRAM) technology is fast maturing to production levels. Main advantages of PRAM are non-volatility, byte addressability, in-place programmability, low-power operation, and higher write endurance than that of current flash memories. However, the relatively low write bandwidth and the less-than-desirable write endurance(More)
beta-Amyloid(1-42) (A beta 42), a major component of amyloid plaques, accumulates within pyramidal neurons in the brains of individuals with Alzheimer's disease (AD) and Down syndrome. In brain areas exhibiting AD pathology, A beta 42-immunopositive material is observed in astrocytes. In the present study, single- and double-label immunohistochemistry were(More)
The number of cores in a single chip multiprocessor is expected to grow in coming years. Likewise, aggregate on-chip cache capacity is increasing fast and its effective utilization is becoming ever more important. Furthermore, available cores are expected to be underutilized due to the power wall and highly heterogeneous future workloads. This trend makes(More)
A key design issue for chip multiprocessors (CMPs) is how to exploit the finite chip area to get the best system throughput.The most dominant area-consuming components in a CMP are processor cores and caches today.There is an important trade-off between the number of cores and the amount of cache in a single CMP chip.If we have too few cores, the system(More)
This paper considers the use of constrained minimum crest factor multisine signals as inputs for plant-friendly identification testing of chemical process systems. The methodology presented here effectively integrates operating restrictions, information-theoretic requirements, and state-of-the-art optimization techniques to design minimum crest factor(More)
Highly interactive systems are ill-conditioned and highly sensitive to model uncertainty , which imposes limitations to achievable closed-loop performance. In this paper, the goal is to develop an identification testing framework meaningful to highly interactive systems based on the application of constrained minimum crest factor multisine signals. "(More)
A silicon nanowire-FET (SiNAWI-FET) for high performance logic device with consideration of current direction effects and terabit non-volatile memory (NVM) device using an 8nm SiNAWI-NVM with oxide/nitride/oxide (ONO) and omega-gate structure is reported for the first time. N-and P-channel SiNAWI-FET showed the highest driving current on (110)/<110> crystal(More)
Inosine, a breakdown product of adenosine, has recently been shown to exert immunomodulatory and neuroprotective effects. We show here that the oral administration of inosine has antidepressant-like effects in two animal models. Inosine significantly enhanced neurite outgrowth and viability of primary cultured neocortical neurons, which was suppressed by(More)
The slow speed of conventional execution-driven architecture simulators is a serious impediment to obtaining desirable research productivity. This paper proposes and evaluates a fast manycore processor simulation framework called two-phase trace-driven simulation (TPTS), which splits detailed timing simulation into a trace generation phase and a trace(More)
In sub-90nm technologies, more frequent hard faults pose a serious burden on processor design and yield control. In addition to manufacturing-time chip repair schemes, microarchitectural techniques to make processor components resilient to hard faults become increasingly important. This paper considers defects in cache memory and studies their impact on(More)