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The phase-change random access memory (PRAM) technology is fast maturing to production levels. Main advantages of PRAM are non-volatility, byte addressability, in-place programmability, low-power operation, and higher write endurance than that of current flash memories. However, the relatively low write bandwidth and the less-than-desirable write endurance(More)
This paper considers the use of constrained minimum crest factor multisine signals as inputs for plant-friendly identification testing of chemical process systems. The methodology presented here effectively integrates operating restrictions, information-theoretic requirements, and state-of-the-art optimization techniques to design minimum crest factor(More)
Highly interactive systems are ill-conditioned and highly sensitive to model uncertainty , which imposes limitations to achievable closed-loop performance. In this paper, the goal is to develop an identification testing framework meaningful to highly interactive systems based on the application of constrained minimum crest factor multisine signals. "(More)
A silicon nanowire-FET (SiNAWI-FET) for high performance logic device with consideration of current direction effects and terabit non-volatile memory (NVM) device using an 8nm SiNAWI-NVM with oxide/nitride/oxide (ONO) and omega-gate structure is reported for the first time. N-and P-channel SiNAWI-FET showed the highest driving current on (110)/<110> crystal(More)
Credits  Parts of the work presented in this talk are from the results obtained in collaboration with students and faculty at the Recent multicore design trends  Modular designs based on relatively simple cores • Easier to validate (a single core) • Easier to scale (the same validated design replicated multiple times) • Due to these reasons, future "(More)
Inosine, a breakdown product of adenosine, has recently been shown to exert immunomodulatory and neuroprotective effects. We show here that the oral administration of inosine has antidepressant-like effects in two animal models. Inosine significantly enhanced neurite outgrowth and viability of primary cultured neocortical neurons, which was suppressed by(More)
In sub-90nm technologies, more frequent hard faults pose a serious burden on processor design and yield control. In addition to manufacturing-time chip repair schemes, microarchitectural techniques to make processor components resilient to hard faults will become increasingly important. This paper considers defects in cache memory and studies their impact(More)
The slow speed of conventional execution-driven architecture simulators is a serious impediment to obtaining desirable research productivity. This paper proposes and evaluates a fast manycore processor simulation framework called Two-Phase Trace-driven Simulation (TPTS), which splits detailed timing simulation into a trace generation phase and a trace(More)
A key design issue for chip multiprocessors (CMPs) is how to exploit the finite chip area to get the best system throughput. The most dominant area-consuming components in a CMP are processor cores and caches today. There is an important trade-off between the number of cores and the amount of cache in a single CMP chip. If we have too few cores, the system(More)
This paper proposes and studies a distributed L2 cache management approach through page-level data to cache slice mapping in a future processor chip comprising many cores. L2 cache management is a crucial multicore processor design aspect to overcome non-uniform cache access latency for high program performance and to reduce on-chip network traffic and(More)