Hyo-Joong Suh

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Abstract We propose a power-aware ECC (Error Correction Code) register without hurting the reliability of data caches. The ECC register replaces the complicated ECC array used in traditional data caches. While the traditional ECC in the ECC array is dedicated to one cache line, the proposed ECC register is shared by all the cache lines, which significantly(More)
This study introduces a novel conservative modulation and coding scheme to minimize and stabilize the delay incurred during the process of electrocardiogram (ECG) transmission over a wireless medium, while maintaining the desired level of the ECG pattern quality required for improving the chance of its interpretation. A machine-type communication system is(More)
Sung Woo Chung is the designated presenter and he will attend the conference should his paper accepted Primary technical subject area : A. Computer Architecture and Super Computing 1. Introduction As microprocessors speeds continue to improve at a very fast rate the bandwidth requirements for system level interconnections in multiprocessor systems rule out(More)
The performances of multiprocessor systems mainly rely on the processor clock speed and the memory latency. As the processors speed up rapidly, the memory latency becomes a major performance bottleneck in multiprocessor systems. In this paper, we propose a dual-link interconnection topology and its effective routing scheme to reduce the remote memory(More)
This paper proposes a rate adjustment scheme for inbound data traffic on a virtualized host. Most prior studies on network virtualization have only focused on outbound traffic, yet many cloud applications rely on inbound traffic performance. The proposed scheme adjusts the inbound rates of virtual network interfaces dynamically in proportion to the(More)