Hyesoon Kim

Publications133
h-index30
Citations4,573
Highly Influential Citations405
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  • Publications
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An analytical model for a GPU architecture with memory-level and thread-level parallelism awareness
TLDR
GPU architectures are increasingly important in the multi-core era due to their high number of parallel processors. Expand
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Qilin: Exploiting parallelism on heterogeneous multiprocessors with adaptive mapping
TLDR
We propose adaptive mapping, a fully automatic technique to map computations to processing elements on a CPU+GPU machine. Expand
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An integrated GPU power and performance model
GPU architectures are increasingly important in the multi-core era due to their high number of parallel processors. Performance optimization for multi-core processors has been a challenge for… Expand
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Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers
TLDR
This paper proposes a mechanism that incorporates dynamic feedback into the design of the prefetcher to increase the performance improvement provided by prefetching as well as to reduce the negative performance impact of large main memory latencies. Expand
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Inferring Fine-grained Control Flow Inside SGX Enclaves with Branch Shadowing
TLDR
We explore a new, yet critical, side-channel attack, branch shadowing, that reveals fine-grained control flows (branch granularity) in an enclave. Expand
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Transparent Hardware Management of Stacked DRAM as Part of Memory
TLDR
This paper proposes a practical, low-cost architectural solution to efficiently enable using large fast memory as Part-of-Memory (PoM) seamlessly, without the involvement of the OS. Expand
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SD3: A Scalable Approach to Dynamic Data-Dependence Profiling
TLDR
We propose a scalable approach to data-dependence profiling that addresses both runtime and memory overhead in a single framework by parallelizing the dependence profiling step itself. Expand
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GraphPIM: Enabling Instruction-Level PIM Offloading in Graph Computing Frameworks
TLDR
We present GraphPIM, a full-stack solution for graph computing that achieves higher performance using PIM functionality. Expand
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Many-Thread Aware Prefetching Mechanisms for GPGPU Applications
TLDR
We consider the problem of how to improve memory latency tolerance in massively multithreaded GPGPUs when the thread-level parallelism of an application is not sufficient to hide memory latency. Expand
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GraphBIG: understanding graph computing in the context of industrial solutions
TLDR
We present GraphBIG, a graph computing benchmark suite inspired by IBM System G project, a benchmark suite that covers major graph computation types and data sources. Expand
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