Hwann-Kaeo Chiou

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This paper presents divide-by-2 and divide-by-3 injection-locked frequency dividers (ILFDs) using a Darlington cell in a TSMC 0.18- μm CMOS process. The Darlington cell has higher transconductance than the traditional cross-coupled common source cell for free-running oscillator that reduces the power consumption of ILFDs. Besides, an LC resonance(More)
This study presents an asymmetric broadside coupled balun with low-loss broadband characteristics for mixer designs. The correlation between balun impedance and a 3D multilayer CMOS structure are discussed and analyzed. Two asymmetric multilayer meander coupled lines are adopted to implement the baluns. Three balanced mixers that comprise three miniature(More)
This paper presents symmetric offset stack Marchand single and dual baluns that are designed, analyzed, and implemented in a 0.18-μm CMOS process to verify the feasibility. Both single and dual baluns achieve measured bandwidths (BWs) of over 110% and 90%, and insertion losses of less than 4.4 and 7.4 dB at 38 GHz. The amplitude imbalance and phase(More)
A high-gain gate-pumped down-conversion mixer at 60 GHz is realized in a standard 90-nm CMOS process. The proposed mixer adopted a Darlington cell and a microstrip-line Lange coupler to yield wide 3-dB bandwidth from 5 to 65 GHz. The measured performance demonstrates a conversion gain (CG) of 6 dB at 4.2-mW power consumption. The maximum CG is 6.5 dB at 36(More)
This paper proposes a high-efficiency dual-band on-chip rectifying antenna (rectenna) at 35 and 94 GHz for wireless power transmission. The rectenna is designed in slotline (SL) and finite-width ground coplanar waveguide (FGCPW) transmission lines in a CMOS 0.13-μm process. The rectenna comprises a high gain linear tapered slot antenna (LTSA), an(More)
A 5 GHz double balanced mixer (DBM) is implemented in standard 90 nm CMOS low-power technology. A novel low-voltage self-bias current reuse technique is proposed in the RF transconductance stage to obtain better third-order intermodulation intercept point (IIP ) and conversion gain (CG) when considering the process variations. The DBM achieves a CG of 12(More)
This paper proposes a microwatt source-driven down-conversion mixer with broadband asymmetrical broadside-coupled baluns in a 90-nm CMOS low-power process. The forward body biased (FBB) technique reduces the threshold voltage (V<sub>TH</sub>) and supply voltage for operation in the near weak inversion region in millimeter-wave mixer designs. To effectively(More)
This brief proposes a third-order active notch filter for an interferer-rejection (IR) ultrawideband low-noise amplifier (LNA) in a 0.18-μm complementary metal–oxide–semiconductor process. The design formulas are derived by considering the minimum power dissipation for the active notch filter that provides proper selections of the device size, the bias(More)
A 28 GHz sub-harmonically pumped passive down conversion mixer fabricated in a 0.18-mum CMOS process is demonstrated. A low power fully differential LO frequency doubler is designed to generate at near half RF frequency. The proposed sub-harmonically pumped passive mixer has advantages in low power consumption, high fundamental frequency suppression, and(More)