Hwan-Seok Yeo

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An all-digital 90deg phase-shift DLL is proposed for 1.6 Gbps DDR interface by using a loop-embedded DCC and a binary phase detector with the lock range extended to 0~4pi radians. The DCC has a small delay and the fixed rising-edge property for loop-embedding. The chip fabricated with a 0.13 um CMOS process gives the DLL data rate of 667 Mbps~1.6 Gbps and(More)
A static and a dynamic D-type flip-flops (D-FFs) using InP heterojunction bipolar transistors (HBTs) were analyzed. Both the static and dynamic D-FFs employed conventional read/latch structure, however the dynamic D-FF had smaller latch current than the read current to improve the bandwidth. The static D-FF exhibited the maximum operating bit rate of 12(More)
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