Hung-Fai Stephen Law

Learn More
Previously the gate matrix technique was used to lay out the RALU section of a CMOS 32-bit CPU chip. It took 1.2 Engineer-Years to complete the layout of the RALU that contained more than 20,000 transistors with multiple-bus structure. The average packing density was 840 μm2 per transistor in 2.5 μm design rules. Recently we have applied the gate(More)
The dynamics of today's electronics industry introduces enormous pressure on chip designers to come up with chip designs in a very limited time. This is due partly to the short life cycle of application specific products in the marketplace. The availability of powerful graphics processors and microprocessors with processing powers comparable to(More)
  • 1