Hun-Seung Oh

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As the complexity of high-performance microprocessor increases,functional verification becomes more and more difficultand RTL simulation emerges as the bottleneck of thedesign cycle.In this paper, we suggest C language-based designand verification methodology to enhance the simulationspeed instead of the conventional HDL-based methodologies.RTL C model(More)
As the complexity of high-performance microprocessor increases, functional verification becomes more difficult and emerges as the bottleneck of the design cycle. In this paper, we suggest a functional verification methodology, especially for the compatible microprocessor design. To guarantee the perfect compatibility with previous microprocessors, we(More)
| As the complexity of high-performance microprocessor increases, functional veri cation becomes more di cult and emerges as the bottleneck of the design cycle. In this paper, we suggest a functional veri cation methodology, especially for the compatible microprocessor design. To guarantee the perfect compatibility with previous microprocessors, we(More)
−This paper proposes a network processor especially optimized for content switching. With 2Gbps port capability, it integrates packet processor cluster, content-based classification engine and traffic manager on a single chip. A switch fabric architecture is also designed for scale-up of the network processor’s capability over hundreds gigabit bandwidth.(More)
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